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2.6.9
Timer Timing
Table 39. Timer Timing
TIMERx frequency
TIMERx Input high phase
TIMERx Output low phase
Characteristics
Symbol
T TMREFCLK
T TMCH
T TMCL
Min
10.0
4.0
4.0
Unit
ns
ns
ns
Figure 23 shows the timer input AC timing
T TMREFCLK
T TMCH
T TMCL
TIMERx (Input)
Figure 23. Timer Timing
2.6.10
Ethernet Timing
This section describes the AC electrical characteristics for the Ethernet interface.
There are programmable delay units (PDU) that should be programmed differently for each Interface to meet timing. There is
a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8144 Reference
Manual .
2.6.10.1
Management Interface Timing
Table 40. Ethernet Controller Management Interface Timing
Characteristics
Symbol
Min
Max
Unit
ETHMDC to ETHMDIO
delay 2
t MDKHDX
10
70
ns
ETHMDIO to ETHMDC rising edge setup time
ETHMDC rising edge to ETHMDIO hold time
t MDDVKH
t MDDXKH
7
0
—
—
ns
ns
Notes:
54
1.
2.
Program the ETHMDC frequency (f MDC ) to a maximum value of 2.5 MHz (400 ns period for t MDC ). The value depends on the
source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz, to
achieve f MDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8144 Reference Manual for
configuration details.
The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of
333 MHz, the delay is 58 ns.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
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